It is known that conventional integrated circuit (IC) fabrication processes utilize a so-called “Manhattan geometry” to form the circuits and interconnects associated with an IC. In such a geometry, horizontal and vertical wires formed at 90° (degrees) to one another are used to connect points across the IC or chip, while a 45° wire is typically used in corners of the chip and, in some cases, in the internal section or interconnect, so that distances can be reduced. However, in order to implement these wires or edges in a Manhattan IC, one must adhere to the so-called “litho step.” The litho step is defined as the resolution movement allowed in the x or y direction. For example, in 0.35 μm (micrometers), 0.25 μm and 0.18 μm wire sizes, the resolution step is 0.02 μm. Thus, to make a horizontal wire as shown in FIG. 1, a number of these litho steps are combined to form the horizontal wire. It is to be understood that W and L are multiples of the litho step. As shown in FIG. 1, a litho step includes the horizontal, or x, movement denoted by the arrow labeled A and the vertical, or y, movement denoted by the arrow labeled B.
However, when a 45° wire or edge is made using conventional Manhattan geometry techniques, the litho step causes the edges to become wavy, as illustrated in FIG. 2. This causes several problems. First, the database used to store the data associated with the fabrication of an IC that includes these edges increases significantly as compared to a database associated with the fabrication of only horizontal and vertical wires. The straight edges can be combined to reduce memory storage, but for 45° edges, the step of 0.02 μm in wires where W=0.3 μm and L=10,000 μm can be severe. Second, the extraction of this wire causes problems since the W and L are not well-defined, as illustrated by the waviness of the lines in FIG. 2. When this wire is a poly silicon gate, the extraction in a transistor causes most Computer Aided Design or CAD tools to give fictitious results, as well as increase the database size associated with the extraction. Third, the write time associated with 45° angles or lines is longer because of the grain size or “litho size” effect.
Thus, it would be advantageous to have a technique for forming a 45° edge that allows wires to crisscross the chip, i.e., to traverse the entire chip surface rather than just the corners as in the conventional Manhattan geometry, and therefore save on interconnect distances while avoiding the waviness problem associated with the litho step. For example, as shown in FIG. 3, assume that two points A and B in the chip must communicate with one another. Using conventional techniques, the Manhattan method would allow a horizontal wire along x and a vertical wire along y. This would give a total interconnect distance between A and B of x+y.
By drawing a wire along the hypotenuse, the interconnect distance is √{square root over (x2+y2)} which is less than x+y. In the case where x=y, the hypotenuse is √{square root over (2x2)} while the distance between A and B in accordance with the conventional technique would be 2x. Thus, the distance is reduced by
                    2            ⁢      x              2      ⁢      x        =      1          2      or 0.707. This is about 30% (percent) less distance than the distance associated with traversing only the edges of the triangle.
Unfortunately, several problems have prevented this technique from being previously realized. For example, the three problems described above are impediments to the use of such a technique. Further, once a wire runs from one corner of the chip to the other, as illustrated in FIG. 3 by wire AB, all interconnects on this level are blocked by the wire. Thus, interconnects on this level must be made in smaller Manhattan lengths or in 45° edges. But, as explained above, if this is done: (1) write time will increase enormously; (2) CAD extraction will be a problem; and (3) the data storage and file size will be large.
Accordingly, there is a need for IC fabrication techniques capable of forming a 45° wire, or a wire at another angle other than 0° or 90°, in an IC which overcome the problems described above such that wires so formed can crisscross the chip, and thus save on interconnect distances while avoiding the waviness problem associated with the litho step.